ID Timestamp Commit Sim Build fmax Benchmark DP16KD EHXPLLL MULT18X18D TRELLIS_COMB TRELLIS_FF TRELLIS_RAMW
55 2022-06-19 20:26:08

develop → 49142817

Generate badges with f_max, DMIPS

PASS PASS
clk_sys 50.0 67.1
hdmi_video.clk_125MHz 125.0 278.4
hdmi_video.clk_25MHz 25.0 173.9
20.8 DMIPS
0.42 DMIPS / MHz
23/208
(414 kbit)
2/4 4/156 6900/83640 2504/83640 128/10455
54 2022-06-19 20:08:04

develop → 52d95486

Display specific failing cocotb testcases

PASS PASS
clk_sys 50.0 67.1
hdmi_video.clk_125MHz 125.0 278.4
hdmi_video.clk_25MHz 25.0 173.9
20.8 DMIPS
0.42 DMIPS / MHz
23/208
(414 kbit)
2/4 4/156 6900/83640 2504/83640 128/10455
47 2022-06-19 19:25:49

ci → 2fd9c765

CI

FAIL PASS
clk_sys 50.0 67.1
hdmi_video.clk_125MHz 125.0 278.4
hdmi_video.clk_25MHz 25.0 173.9
20.8 DMIPS
0.42 DMIPS / MHz
23/208
(414 kbit)
2/4 4/156 6900/83640 2504/83640 128/10455
45 2022-06-17 19:45:46

develop → 83455fb1

Add rudimentary interrupt control

PASS PASS
clk_sys 50.0 67.1
hdmi_video.clk_125MHz 125.0 278.4
hdmi_video.clk_25MHz 25.0 173.9
20.8 DMIPS
0.42 DMIPS / MHz
23/208
(414 kbit)
2/4 4/156 6900/83640 2504/83640 128/10455
43 2022-06-17 19:33:18

develop → d13cd822

CPU: Enable 'mtvec' CSR

PASS PASS
clk_sys 50.0 63.1
hdmi_video.clk_125MHz 125.0 260.4
hdmi_video.clk_25MHz 25.0 186.0
20.8 DMIPS
0.42 DMIPS / MHz
23/208
(414 kbit)
2/4 4/156 6783/83640 2494/83640 128/10455
42 2022-06-17 17:24:33

develop → e5344a70

Add some placeholder video CSRs

PASS PASS
clk_sys 50.0 65.8
hdmi_video.clk_125MHz 125.0 283.8
hdmi_video.clk_25MHz 25.0 189.5
20.8 DMIPS
0.42 DMIPS / MHz
23/208
(414 kbit)
2/4 4/156 6692/83640 2461/83640 128/10455
41 2022-06-06 20:16:26

develop → 4fc4b257

Resolve most Verilator warnings

PASS PASS
clk_sys 50.0 66.0
hdmi_video.clk_125MHz 125.0 270.6
hdmi_video.clk_25MHz 25.0 188.2
20.8 DMIPS
0.42 DMIPS / MHz
23/208
(414 kbit)
2/4 4/156 6609/83640 2461/83640 128/10455
40 2022-06-06 20:16:14

develop → 77699e5e

Trade some FFs for less COMB

PASS PASS
clk_sys 50.0 65.0
hdmi_video.clk_125MHz 125.0 283.8
hdmi_video.clk_25MHz 25.0 178.6
20.8 DMIPS
0.42 DMIPS / MHz
23/208
(414 kbit)
2/4 4/156 6699/83640 2461/83640 128/10455
39 2022-06-06 19:17:27

develop → 9ac6d3ad

Trade boot ROM latency for faster critical path

PASS PASS
clk_sys 50.0 65.9
hdmi_video.clk_125MHz 125.0 239.9
hdmi_video.clk_25MHz 25.0 184.4
20.8 DMIPS
0.42 DMIPS / MHz
23/208
(414 kbit)
2/4 4/156 6594/83640 2445/83640 128/10455
38 2022-06-06 17:58:05

develop → d772c4ee

Adjust bootloader in line with recommended I-cache

PASS PASS
clk_sys 50.0 60.8
hdmi_video.clk_125MHz 125.0 277.2
hdmi_video.clk_25MHz 25.0 186.7
20.8 DMIPS
0.42 DMIPS / MHz
23/208
(414 kbit)
2/4 4/156 6714/83640 2470/83640 128/10455
37 2022-06-06 16:43:40

develop → 1d70f871

Use Cheby-generated CSR module

PASS PASS
clk_sys 50.0 64.6
hdmi_video.clk_125MHz 125.0 260.2
hdmi_video.clk_25MHz 25.0 189.8
20.8 DMIPS
0.42 DMIPS / MHz
23/208
(414 kbit)
2/4 4/156 6434/83640 2470/83640 128/10455
36 2022-06-06 14:59:14

develop → 967feefe

Recompile Dhrystone binary

PASS PASS
clk_sys 50.0 59.4
hdmi_video.clk_125MHz 125.0 262.5
hdmi_video.clk_25MHz 25.0 180.1
20.8 DMIPS
0.42 DMIPS / MHz
23/208
(414 kbit)
2/4 4/156 6596/83640 2352/83640 128/10455
35 2022-06-06 14:50:56

develop → d71663d6

Use Cheby to generate CSR declarations

PASS PASS
clk_sys 50.0 64.9
hdmi_video.clk_125MHz 125.0 274.3
hdmi_video.clk_25MHz 25.0 194.6
23/208
(414 kbit)
2/4 4/156 6655/83640 2352/83640 128/10455
34 2022-06-06 13:01:55

develop → f89112eb

Fix Verilator include paths

PASS PASS
clk_sys 50.0 61.4
hdmi_video.clk_125MHz 125.0 266.8
hdmi_video.clk_25MHz 25.0 179.9
23/208
(414 kbit)
2/4 4/156 6536/83640 2352/83640 128/10455
33 2022-06-06 12:52:34

develop → 110e0508

TRACE_REG -> UART_STATUS (r) + UART_DATA (w)

? PASS
clk_sys 50.0 61.4
hdmi_video.clk_125MHz 125.0 266.8
hdmi_video.clk_25MHz 25.0 179.9
23/208
(414 kbit)
2/4 4/156 6536/83640 2352/83640 128/10455
32 2022-06-01 20:51:09

develop → 4633aaf8

Correct CPU freq

PASS PASS
clk_sys 50.0 64.2
hdmi_video.clk_125MHz 125.0 291.9
hdmi_video.clk_25MHz 25.0 172.5
20.8 DMIPS
0.42 DMIPS / MHz
23/208
(414 kbit)
2/4 4/156 6548/83640 2352/83640 128/10455
31 2022-06-01 20:34:35

develop → 88f73702

Bump system clock to 50 MHz

FAIL PASS
clk_sys 50.0 64.2
hdmi_video.clk_125MHz 125.0 291.9
hdmi_video.clk_25MHz 25.0 172.5
23/208
(414 kbit)
2/4 4/156 6548/83640 2352/83640 128/10455
30 2022-06-01 20:04:29

develop → 8778136f

Bump system clock to 50 MHz

FAIL PASS
clk_sys 50.0 62.0
hdmi_video.clk_125MHz 125.0 213.7
hdmi_video.clk_25MHz 25.0 198.5
23/208
(414 kbit)
2/4 4/156 6514/83640 2352/83640 128/10455
29 2022-06-01 19:02:55

develop → d35647aa

CPU: Enable M extension

PASS PASS
clk_sys 25.0 62.6
hdmi_video.clk_125MHz 125.0 272.6
hdmi_video.clk_25MHz 25.0 190.9
10.4 DMIPS
0.42 DMIPS / MHz
23/208
(414 kbit)
2/4 4/156 6395/83640 2349/83640 128/10455
28 2022-06-01 18:57:26

develop → b1267da2

Rename boot/ -> firmware/

PASS PASS
clk_sys 25.0 62.8
hdmi_video.clk_125MHz 125.0 218.6
hdmi_video.clk_25MHz 25.0 160.7
10.4 DMIPS
0.42 DMIPS / MHz
23/208
(414 kbit)
2/4 0/156 6119/83640 1991/83640 128/10455
27 2022-06-01 16:54:19

develop → a8be9eae

builds.html: Show also DP16KD usage

PASS PASS
clk_sys 25.0 62.8
hdmi_video.clk_125MHz 125.0 218.6
hdmi_video.clk_25MHz 25.0 160.7
10.4 DMIPS
0.42 DMIPS / MHz
23/208
(414 kbit)
2/4 0/156 6119/83640 1991/83640 128/10455
26 2022-05-31 23:18:46

develop → 84cc4fbf

builds.html: Show also DP16KD usage

PASS PASS
clk_sys 25.0 62.8
hdmi_video.clk_125MHz 125.0 218.6
hdmi_video.clk_25MHz 25.0 160.7
10.4 DMIPS
0.42 DMIPS / MHz
23/208
(414 kbit)
2/4 0/156 6119/83640 1991/83640 128/10455
25 2022-05-31 23:06:24

develop → c0ef15de

Dhrystone result on builds.html

PASS PASS
clk_sys 25.0 62.8
hdmi_video.clk_125MHz 125.0 218.6
hdmi_video.clk_25MHz 25.0 160.7
10.4 DMIPS
0.42 DMIPS / MHz
23/208
(414 kbit)
2/4 0/156 6119/83640 1991/83640 128/10455
21 2022-05-31 20:14:51

develop → a7f32f05

Adjust Verilator flags

? PASS
clk_sys 25.0 62.8
hdmi_video.clk_125MHz 125.0 218.6
hdmi_video.clk_25MHz 25.0 160.7
23/208
(414 kbit)
2/4 0/156 6119/83640 1991/83640 128/10455
20 2022-05-29 20:45:14

develop → 738af357

Fix critical flaw in setting of SDRAM DQM signals

FAIL PASS
clk_sys 25.0 65.8
hdmi_video.clk_125MHz 125.0 262.1
hdmi_video.clk_25MHz 25.0 184.1
23/208
(414 kbit)
2/4 0/156 5813/83640 1991/83640 128/10455
19 2022-05-29 20:44:23

develop → 4e6ae803

Video_Ctrl: stop fetching framebuffer after 240 li

FAIL PASS
clk_sys 25.0 59.7
hdmi_video.clk_125MHz 125.0 244.1
hdmi_video.clk_25MHz 25.0 184.7
23/208
(414 kbit)
2/4 0/156 6165/83640 1991/83640 128/10455
18 2022-05-29 12:23:56

develop → 71bee6e0

Add Verilator test for framebuffer

FAIL PASS
clk_sys 25.0 62.7
hdmi_video.clk_125MHz 125.0 224.2
hdmi_video.clk_25MHz 25.0 201.3
23/208
(414 kbit)
2/4 0/156 5944/83640 1981/83640 128/10455
14 2022-05-28 20:20:39

develop → cd33c982

Build boot code with CMake

PASS PASS
clk_sys 25.0 62.7
hdmi_video.clk_125MHz 125.0 224.2
hdmi_video.clk_25MHz 25.0 201.3
23/208
(414 kbit)
2/4 0/156 5944/83640 1981/83640 128/10455
12 2022-05-28 20:03:16

develop → 6a02cba9

boot_syn.vh now goes under /build

PASS PASS
clk_sys 25.0 62.7
hdmi_video.clk_125MHz 125.0 224.2
hdmi_video.clk_25MHz 25.0 201.3
23/208
(414 kbit)
2/4 0/156 5944/83640 1981/83640 128/10455
11 2022-05-28 19:04:06

develop → 86be3812

Dump framebuffer from Verilator testbench

PASS PASS
clk_sys 25.0 62.7
hdmi_video.clk_125MHz 125.0 224.2
hdmi_video.clk_25MHz 25.0 201.3
23/208
(414 kbit)
2/4 0/156 5944/83640 1981/83640 128/10455
10 2022-05-28 14:37:15

develop → be8566a4

Refactor SDRAM controller to not use tri-state bus

PASS PASS
clk_sys 25.0 62.7
hdmi_video.clk_125MHz 125.0 224.2
hdmi_video.clk_25MHz 25.0 201.3
23/208
(414 kbit)
2/4 0/156 5944/83640 1981/83640 128/10455
9 2022-05-28 14:22:28

develop → b0d7ca40

Track CI results in SQL database

PASS PASS
clk_sys 25.0 64.0
hdmi_video.clk_125MHz 125.0 299.1
hdmi_video.clk_25MHz 25.0 185.5
23/208
(414 kbit)
2/4 0/156 5899/83640 1981/83640 128/10455
8 2022-05-28 14:15:17

ci → b73ad9e3

Fix simulation

PASS FAIL
7 2022-05-28 14:14:39

ci → 6209a49d

Break synthesis

FAIL FAIL
6 2022-05-28 14:08:48

ci → 9a278143

Intentional simulation failure

FAIL PASS
clk_sys 25.0 64.0
hdmi_video.clk_125MHz 125.0 299.1
hdmi_video.clk_25MHz 25.0 185.5
23/208
(414 kbit)
2/4 0/156 5899/83640 1981/83640 128/10455
5 2022-05-28 14:00:17

ci → b5bf28a3

Track CI results in SQL database

PASS PASS
clk_sys 25.0 64.0
hdmi_video.clk_125MHz 125.0 299.1
hdmi_video.clk_25MHz 25.0 185.5
23/208
(414 kbit)
2/4 0/156 5899/83640 1981/83640 128/10455
4 2022-05-28 13:54:36

ci → ea8a5f3e

Track CI results in SQL database

PASS PASS
clk_sys 25.0 64.0
hdmi_video.clk_125MHz 125.0 299.1
hdmi_video.clk_25MHz 25.0 185.5
23/208
(414 kbit)
2/4 0/156 5899/83640 1981/83640 128/10455